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• <H4> Contact Us, Make An Enquiry, or Request Free Trials
• <H2> Synaptic Laboratories Limited provides innovative Soft IP for programmable (FPGA) chips, to enable better products for a brighter future
• <H4>  Soft IP Products To Increase Your Project Viability:-1. Less circuit area for your project.  Fit more on your chosen Intel Altera chip, or try for a cheaper (smaller or lower grade) chip.2. Higher performance for software and bus master peripherals3. Higher clock speeds4. Easier place and route and timing sign off5. Essential 'low cost' security capabilities, to satisfy government legislation and insurance requirements,  and to protect your IP and your customers loyalty and safety Failure to build in low cost, viable and readily available security solutions exposes developers, FPGA product makers and end users to government and insurance liability in the event of breaches and data theft!  It also exposes your hard won project IP to theft and counterfeit.  The fines and costs of recovery can FAR exceed the zero to very low hardware costs of adding security.  Download the free '5 Essential Base-line Hardware Security Controls' brochure from ISDF16 below.6. We bundle our IP together (and provide labs) to save you time, to fast track your project to better results.LATEST INFORMATION ON THE EXCITING HYPERMAX DEVELOPMENT BOARD. HyperMAX is the ONLY HyperBus development board that supports Cypress HyperRAM and HyperFlash with an Intel FPGA.  Exceptional hardware cost savings and performance gains are possible. This board employs Synaptic Labs HyperBus memory controller, the ONLY controller optimised for Intel FPGA. DOWNLOAD THE SHORT HyperMAX INFORMATION BROCHURE here .  Excellent results for area constrained and IoT designs! 
• <H4> The exciting HyperMAX development board is available from Synaptic Labs partner, devboards GmbH. More information on the devboards website here .   
• <H4> 2017 NEWS FLASH: EBV Elektronik (Avnet) selects Synaptic Labs' soft IP to win very significant gains in their exciting HyperMAX development board GAINS WON by EBV Elektronik from Synaptic Labs' IP include ~55% higher clock speeds, more debug capabilities, up to ~1.8x faster software performance, and 20% less total SRAM,  all while REDUCING the total Qsys project circuit area by 30%.  We are constantly improving on these results.  Read more here .  Contact us to freely explore how Synaptic Labs' soft IP can transform your project.
• <H4> Contact form  
• <H4> 2017 NEWS FLASH: EBV Elektronik (Avnet) selects Synaptic Labs' Cypress HyperRam and HyperFlash programmer and cache technology (CMS-T003).  EBV won ~20% reduction in total circuit area for their exciting Intel Max10 / Cypress Hyper memories demonstration project on the latest DevBoards development board.  Contact us for more information.
• <H4> 2017 NEWS FLASH: Synaptic Labs' tiny AES inline memory encryptor (SMEM-T001) that was included in our presentation at ISDF16 in Frankfurt is now available on the Intel Altera Design Cloud at this link .  This simple lab demonstrates how easy it is to achieve secure boot and secure execution of code (XiP) from off-chip flash.   This lab can be easily adapted for use with any COTS development board.  See more information further below.
• <H4> 2017 NEWS FLASH: Synaptic Labs' advances a new controller for the exciting Cypress HyperRam and HyperFlash. Expect ~80% reduction in controller circuit area, no SRAM required, and far higher performance. It now costs LESS hardware resources to support HyperRAM and HyperFlash in FPGA than conventional DDR and EPCQ flash.  Read more here . Contact us for more information about employing this extremely efficient HyperBus controller in your project. 
• <H4> Contact form   
• <H4> 2017 NEWS FLASH: Synaptic Labs' announces its new solution to achieve cryptographic authentication of firmware stored on EPCQ memory before the firmware is executed.  The hardware cost of authentication is reduced from 64 to only 4 SROM.  Contact us for more information.
• <H4> 2016 NEWS FLASH:  Synaptic Labs' opened the hardware security session at Intel's annual event for partners and customers, ISDF16 in Frankfurt.  Synaptic Labs' presentation focussed on the 5 ESSENTIAL (base-line) hardware security controls that are readily available today, at zero to very low hardware cost, for soft and hard (ARM) processor cores in FPGA devices.  These 5 essential hardware security controls specifically assist FPGA designers and corporations to satisfy the essential government and insurance requirements, to ensure a reasonable level of security is present, for example the German IT Security Act that requires compliance by 25 July 2017 at the latest.
• <H4> Increase your project's SECURITY to also protect your investment in your project, and your customers loyalty.  Also to be positioned to win a bigger share of the $Trillion that is expected to be spent globally on cybersecurity over the next 5 years.  
• <H4> SYNAPTIC LABS' PRODUCTS ARE AVAILABLE FOR FREE TRIALS NOW
• <H4> INVITATION TO ALL FPGA PROJECT DESIGNERS
• <H2> Product List
• <H3> SMEM-T001:  A very small COTS AES Encryption Module for FPGA FLASH
• <H3> INTER-T002  
• <H3> CMS-T001 -  A FAR SUPERIOR, TINY SOFTWARE ACCELERATOR TO ALWAYS REPLACE THE ALTERA ON-CHIP FLASH ACCELERATOR IN EVERY MAX® 10 PROJECT
• <H3> SRAM-T001.  SUPERIOR SRAM ALLOCATION FOR EVERY ALTERA PROJECT, IN ALL ALTERA DEVICE FAMILIES
• <H3> CMS-T002/3RE-USABLE SYSTEM CACHES / ACCELERATORS, INCLUDING NON-BURST TO BURST CONVERSION - For up to 69x Faster Software and Peripherals. Tiny footprint: Requires only from 50 LE in circuit area, but can actually REDUCE total circuit area up to almost 4x over the cost of using the Qsys burst converter IP
• <H4> Product CMS-T002/3 - Reusable System Caches (System Accelerators) with Non-Burst to Burst Converter
• <H5> Two highly configurable System Caches (System Accelerators) are included in our CMS-T002/3 product.  Their tiny footprint means you can use one or both caches in your design, or use them multiple times throughout your design, matching the best System Cache to each need, to maximise the benefits.
• <H5> CMS-T003 FEATURES AND BENEFITS - A High Performance Write Through System Cache.  For all memories when using the Nios® II/ECONOMY PROCESSOR in all ALTERA Families.  Also Accelerates BUS-MASTER PERIPHERAL access to Memories, with or without a Processor Core.  Also a burst converter that means you can employ the CMS-T003 IP and REDUCE the total circuit area in your design. 
• <H3> Enquire Now - TINY MMU AND MPU FOR EMBEDDED APPLICATIONS: Unique capabilities in tiny circuit area
• <H3> TOWARDS THE ULTIMATE SAFETY AND MIXED-CRITICALITY DESIGNS IN FPGA AND ASIC
• <H5> Information about the technologies being developed within the SSRT project was an invited presentation at the EU Mixed-Criticality Cluster's one day workshop held at the 5 day European event for electronic system design and testing, the "Design, Automation and Test in Europe (Date '16) Conference", Dresden, 14-18 March 2016.  Download the slideshow here.
• <H3> ACCELERATE MESSAGING BETWEEN CORES AND BUS-MASTER PERIPHERALSOur SYSTEM caches (CMS-T002/3) also accelerate messaging for communications/network bus-master peripherals
• <H4> Accelerating Processor To Bus-Master Peripherals Messaging .. and More (CMS-T003 and CMS-T002)
• <H3> REDUCE TOTAL CIRCUIT AREA WITH OUR IPSOME EXAMPLES
• <H4> Quick summary of THREE examples:
• <H3> MAKE SDRAM AND CHEAP OFF-CHIP FLASH MORE VIABLE AND USEFUL IN YOUR DESIGNOur SYSTEM Caches (CMS-T002/3) accelerate software (up to 69x) and bus-master peripherals
• <H3> PROTECT YOUR VULNERABLE OFF-CHIP FLASH - MANAGE THE RISK - IT'S EASYOur very small inline AES encryption module SMEM-T001 removes the main, lowest cost FPGA attack vector.  To protect YOUR valuable IP, and your CUSTOMERS LOYALTY
• <H3> Product SMEM-T001
• <H3> ACCELERATED BUS-MASTER PERIPHERALS IN REDUCED CIRCUIT AREA Our SRAM IP (SRAM-T001) and SYSTEM caches (CMS-T002/3) can also accelerate bus-master peripherals, with or without a core being present
• <H3> SUPERIOR BUS ARBITRATION AND BURST CONVERTERS IN OUR IPTo achieve HIGHER CLOCK SPEEDS and to REDUCE CIRCUIT AREA in your designs
• <H3> STRONGLY ENHANCE PERFORMANCE OF THE SMALLEST NIOS II CORE - UP TO 69X - FOR THE SMALLEST ALTERA DEVICES, OR AS AN EXTRA CORE IN LARGER DEVICES
• <H4> Accelerating Software On The Small Nios II/Economy Core Up To 69x: (CMS-T002/T003)
• <H3> MORE USE CASE EXAMPLES
• <H4>  
• <H4> Chip designers:  Learn more about about What To Expect when using these products here . 
• <H3> What people are saying
• <H3> EU Mixed Criticality Cluster
• <H4> Synaptic Labs' work showcased by the EU Mixed-Criticality Cluster
• <H3> Brian Snow
• <H4> Independent Consultant and Ethics Advisor; inventor and mathematician; cryptologic and security systems architect. Formerly 35 years US NSA (including 12 years as Technical Director) and Member, US National Academy of Sciences Committee, Future Research Goals and Objectives in Foundational Cybersecurity, USA
• <H3> Professor Jacques Patarin
• <H4> Head of Cryptography Department, PRiSM Computer Research Lab, University of Versailles, France
• <H3> Howard Landman
• <H4> Distinguished Chip Design Engineer. Co-designer of the original Berkeley RISC 1 processor and Sony PlayStation 2 "Emotion Engine" (world's first 128bit commercial processor) chips
• <H3> Benjamin Gittins
• <H4> Hardware and Security Architect, Invited Participant at 'closed' Summits including US National Cybersecurity Summit and NATO co-sponsored Dubrovnik Nuclear Conference
• <H3> Mark Bonnici
• <H4> FPGA Design Engineer
• <H3> David Pace
• <H4> Fellow of the British Computer Society, Board Member BCS Malta Branch; Formerly Distinguished Engineer Fujitsu UK; Project Director, ICTGM, Malta
• <H3> Fabian Martins
• <H4> Solutions Architect , Amazon Web Services, FIAP. Formerly Security Manager Scopus and Bradesco Bank, Brazil
• <H3> Login to your account

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• less circuit area12
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• for all device5

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